1. Technical Field
The present invention relates to a thin film transistor that is used in liquid crystal displays of the active matrix system, and a method for manufacturing such a thin film transistor.
2. Prior Art
In a liquid crystal display of the active matrix system that uses thin film transistors, liquid crystals are sealed between a TFT array substrate and a counter substrate overlapping the TFT array substrate with a certain distance. On the TFT array substrate, gate electrodes (Y electrodes) and signal line (X electrodes) are arranged as a matrix, and thin film transistors (TFTs) are disposed on the intersections of the gate electrodes and the data electrodes. The thin film transistors control the voltage impressed to the liquid crystals, and the electrooptic effect of the liquid crystals is utilized to enable displaying.
FIGS. 7A and 7B are diagrams illustrating the structure of a top-gate type thin film transistor. Conventionally known structures of thin film transistors are a top-gate (positive-stagger) type structure and a bottom-gate (inverse-stagger) type structure. The structure of a top-gate type thin film transistor will be described referring to FIG. 7A. The top-gate type thin film transistor comprises a light-shield film 102 provided on an insulating substrate 101 such as a glass substrate, on which an insulating film 103 comprising silicon oxide, SiOx, or silicon nitride, SiNx, is formed. Above the insulating film 103, a drain electrode 104 and a source electrode 105 composed of ITO (indium tin oxide) films are disposed at a predetermined channel distance. An amorphous silicon film (a-Si film) 106, as a semiconductor film, that covers both electrodes is provided; a gate insulating film 107 comprising SiOx or SiNx, is provided above the a-Si film 106; and a gate electrode 108 is provided above the gate insulator film 107, to form an island-shaped region called an a-Si island.
As a process for the manufacture of such a thin film transistor, a process known as 7-PEP (PEP: photo engraving process) structure is generally present. In this 7-PEP structure, after a drain electrode 104 and a source electrode 105 composed of ITO film have been patterned, an a-Si film 106 is formed by CVD (chemical vapor deposition), and is patterned in an island shape. A gate insulating film 107 is then formed by CVD, and is patterned to a desired shape. After that, a gate electrode 108, for example of aluminum (Al), is formed by sputtering, and is patterned to complete a TFT.
However, since such a 7-PEP structure required a large number of process steps, a next-generation 4-PEP structure that requires less process steps has been proposed. In the 4-PEP structure, the gate insulating film 107 and the a-Si film 106 underlying the gate electrode 108 are simultaneously etched. That is, the gate electrode 108, the gate insulating film 107, and the a-Si film 106 are sequentially etched in one patterning step using the plated pattern of the gate electrode 108 as a mask. The 4-PEP structure excels in that the manufacturing process is shortened. FIG. 7A shows the top-gate type thin film transistor produced by the shortened manufacturing process.
Here, if the gate electrode 108, the gate insulating film 107, and the a-Si film 106 are sequentially etched, the distance between the end of the gate electrode 108 and the source and drain electrodes 105 and 104 is much shortened as shown in FIG. 7A. That is, this distance is at largest 0.4 xcexcm, easily causing short-circuiting between the end surface of the gate electrode 108 and the source and drain electrodes 105 and 104 due to surface leakage.
To cope with this problem, the gate electrode 108 is over-etched as shown in FIG. 7B. That is, by over-etching the gate electrode 108 during patterning, a length of about 1.5 xcexcm is secured as shown in FIG. 7B, and by clearing a distance of 1.9 xcexcm (about 2 xcexcm) between the source electrode 105 and the drain electrode 104, short-circuiting due to surface leakage is prevented.
The present applicant has presented Japanese Patent Application No. 11-214603 as a technique related to this shortened manufacturing process. In the present application, techniques for decreasing the number of process steps required in the manufacturing process of thin film transistors, as well as for preventing the generation of an abnormal potential due to leakage current from other data lines.
As described above, the over-etching of the gate line at the time of forming the gate electrode 108 of a top-gate type TFT, and the island cutting using a resist mask (not shown) for forming the gate electrode 108 (etching of the gate insulating film 107 and the a-Si film 106) enable the simplification of the process and the prevention of short-circuiting due to surface leakage.
However, the inventors of the present invention found that the a-Si film 106 and the gate insulator film 107 were exposed in the above-described method might resulting in the occurrence of leakage in the island portion not covered with the gate electrode 108 (floating island region).
FIG. 8 is a diagram that illustrates the states where the floating island portion has been formed. In FIG. 8, a source electrode 111 and a drain electrode 112 are disposed at a predetermined interval, and substantially parallel to each other, and are orthogonal to the gate electrode 110 to form a TFT of a -shaped structure. This TFT of a -shaped structure is described in detail in the above-described Japanese Patent Application No. 11-214603, as a TFT that can prevent undesired current (cross talk) from the adjacent data lines (not shown) with the drain electrode 112 across the gate electrode 110, and can minimize the effect of misalignment.
Here, the circumference region of the gate electrode 110 where the a-Si film 106 and the gate insulator film 107 are exposed is the floating island region 109. Although electrodes are normally disposed above and beneath an a-Si film, the gate electrode 110 is not formed above or beneath the a-Si film 106 as a semiconductor layer that constitutes this floating island portion 109, which is unique as the usage of a-Si. Therefore, voltage is not controlled in this floating island portion 109. That is, the floating island portion 109 is not covered with the gate electrode 110, and is in the state where portions nearer the end are more difficult to be controlled by the gate voltage of the gate electrode 110. The detection of leakage paths using OBIC (optically beam induced current) analysis revealed that leakage occurred due to the voltage between the source electrode 111 and the drain electrode 112 at the portion in the floating island 109 between the source electrode 111 and the drain electrode 112, above which or beneath which the gate electrode 110 is not formed, that is, the hatched area shown in FIG. 8. When leakage occurs at the leakage portion, i.e. the hatched area, voltage cannot be controlled between the source electrode 111 and the drain electrode 112, and the problem such as the discoloration of pixels due to an abnormal voltage has arisen.
FIG. 9 is a graph that shows the volt-ampere characteristic of the TFT of the type shown in FIG. 8 (shaped TFT). The abscissa indicates gate voltage (Vg), and shows the state where the gate electrode 110 is OFF in a range of, for example, xe2x88x925V to xe2x88x927V. The ordinate indicates source-drain current (Ids). Reference character L indicates the distance between the source electrode 111 and the drain electrode 112. As is obvious from FIG. 9, the OFF-current (current when the gate electrode 110 is OFF) rapidly decreases with increase in L. This is because the voltage impressed to the floating island region 109 is switched from source-drain voltage controlled to gate voltage controlled with increase in LOFF/xcex94W from the relationship of the source-drain distance L in the hatched area shown in FIG. 8, LOFF, and the width, xcex94W. For this reason, by increasing L (LOFF), the voltage between the source electrode 111 and the drain electrode 112 does not affect a-Si present in the floating island region 109, but the voltage of the gate electrode 110 affects the a-Si significantly, and leakage voltage can be decreased.
On the other hand, however, when the distance between the source electrode 111 and the drain electrode 112 in the area in which the TFT actually operates, LON, increases, the ON-current required for the TFT to operate actually, ION, decreases in inverse proportion to LON. Since larger value of the ON-current (ION) (for example, the current value when the gate voltage (Vg) shown in FIG. 9 is within a range of 20 to 25V) is preferable, a shorter L (LON) is preferable from the point of view of the ON-current (ION).
Therefore, the present invention is achieved to solve the above technical problems and the object of the present invention is to reduce leakage current in a floating island region formed in a thin film transistor, as well as to maintain the ON-current required for the TFT to operate high.
A thin film transistor to which the present invention is applied comprises a gate electrode disposed above an insulating substrate and formed in a predetermined pattern; a semiconductor layer formed in relation to the pattern of the gate electrode; a pixel electrode formed via the semiconductor layer; and a signal electrode formed via the semiconductor layer and disposed at a predetermined interval from the pixel electrode. The semiconductor layer has a floating island region above which or beneath which the gate electrode is not formed. The pixel and signal electrodes are configured in a manner that the OFF-current channel length formed by the pixel and signal electrodes in the floating island region is longer than the ON-current channel length formed by the pixel and signal electrodes disposed above or beneath the gate electrode.
Here, the signal electrode may be characterized in being disposed at the location for impeding cross talk that flows from adjacent signal lined to the pixel electrode via the semiconductor layer.
Also, a thin film transistor to which the present invention is applied comprises a source electrode and a drain electrode disposed above an insulating substrate at a predetermined interval; a semiconductor layer disposed in relation to the source and drain electrodes; a gate insulator film overlapping the semiconductor layer; and a gate electrode overlapping the gate insulator film. The semiconductor layer has a floating island region above which or beneath which the gate electrode is not formed. The source and drain electrodes are configured in a manner that the channel length formed by the source and drain electrodes in the floating island region is 18 xcexcm or more.
Furthermore, the source and drain electrodes may be characterized in being configured in a manner that the channel length above or beneath the gate electrode is 4 xcexcm or less.
According to the above configuration, the leakage current caused by the floating island region can be restrained, and the required ON-current can be secured sufficiently.
Also, a thin film transistor to which the present invention is applied comprises a gate electrode disposed above an insulating substrate and formed in a predetermined pattern; a semiconductor layer formed in a pattern substantially identical to the pattern of the gate electrode; a source electrode formed via the semiconductor layer; and a drain electrode formed via the semiconductor layer and disposed at a predetermined interval from the source electrode. The source and drain electrodes are configured in a manner that the OFF-current that flows between the source electrode and the drain electrode when the voltage by the gate electrode is OFF is less than 1xc3x9710xe2x88x9212 A, and the ON-current that flows between the source electrode and the drain electrode when the voltage by the gate electrode is 20V or more is 1xc3x9710xe2x88x926 A or more.
Furthermore, the semiconductor layer is characterized in comprising a floating island region above which or beneath which the gate electrode is not formed, and in that the source and drain electrodes are configured in a manner that the OFF-current that flows in the floating island region is less than 1xc3x9710xe2x88x9212 A.
Furthermore, if the source and drain electrodes are characterized in being configured in a manner that the OFF current is less than 1xc3x9710xe2x88x9212 A and the ON-current is 1xc3x9710xe2x88x926 A or more, based on the location of the source and drain electrodes in the floating island region, and the source and drain electrodes disposed above or beneath the gate electrode, the leakage current caused by the floating island region can be impeded, and high TFT characteristics can be secured by the planar shapes of the source and drain electrodes.
In these inventions, it is sufficient if the pixel electrode (source electrode) and the signal electrode (drain electrode) are formed xe2x80x9cabovexe2x80x9d the insulating substrate, and these inventions can be applied to either a top-gate type TFT provided with these electrodes on the insulating substrate side, above which a gate electrode is provided; or a bottom-gate type TFT provided with a gate electrode on the insulating substrate side, above which source and drain electrodes are formed. The expression of xe2x80x9coverlappingxe2x80x9d contains not only overlying, but also underlying, and it is not necessary to contact with each other, but the laminated construction with other materials intervening inbetween may be used.
On the other hand, a liquid crystal display panel to which the present invention is applied comprises gate lines and signal lines arranged in a matrix shape, and thin film transistors arranged on the intersections of said gate lines and signal lines, and operating liquid crystals by applying a voltage to the display electrode. The thin film transistor comprises a gate electrode connected to the gate lines and formed integrally with the gate lines, a drain electrode connected to the signal lines, a source electrode connected to the display electrode disposed at a predetermined interval in relation to the drain electrode, and a semiconductor layer formed between the source and drain electrodes and the gate electrode. The semiconductor layer has a region around the gate electrode and not located above or beneath the gate electrode, and patterned across the region of the thin film transistor and along the gate lines. The drain electrode is configured in a manner to impede the current flowing from adjacent signal lines into the source electrode via the semiconductor layer, and configured in a manner that the length of the channel formed between the drain electrode and the source electrode is long in the region not above or beneath the gate electrode, and is short in the region above or beneath the gate electrode.
If the drain electrode is characterized in being configured in a manner that the channel length in the region not located above or beneath the gate electrode is 18 xcexcm or more, the control by the gate electrode is enhanced even when the gate voltage is OFF, and leakage current caused by the region not located above or beneath the gate electrode can be minimized.
Furthermore, if the drain electrode is characterized in being configured in a manner that the channel length in the region located above or beneath the gate electrode is 4 xcexcm or less, required TFT characteristics can be maintained even when the leakage current is to be minimized.
Furthermore, if the drain electrode is characterized in being configured in a manner to separate the thin film transistor region from the gate line, the generation of an abnormal potential due to cross talk from adjacent signal lines can be prevented.
Furthermore, a method for manufacturing a thin film transistor to which the present invention is applied comprises a light-shield film deposition step of depositing a light-shield film on a substrate; an insulating film formation step of forming an insulating film that covers the light-shield film on the insulating substrate; a pixel and signal electrodes formation step of forming a pixel electrode and a signal electrode on the insulating film; a semiconductor layer and insulating films formation step of for sequentially forming a semiconductor layer and a gate insulator film above the pixel electrode and the signal electrode; a gate electrode deposition step of depositing a metal film for the gate lines and the gate electrode above the gate insulator film; a gate electrode patterning step of providing a resist mask above the metal film for the gate lines and the gate electrode, and for patterning the gate lines and the gate electrode using the resist mask; a semiconductor layer patterning step of patterning the semiconductor layer and the gate insulator film using the resist mask, forming a floating island region around the gate electrode, above which the gate electrode is not disposed; and a step of peeling off the resist mask. This pixel and signal electrodes forming step is characterized in that the signal electrode is formed in the location that separates the regions of the gate lines and the gate electrode patterned in the gate electrode patterning step, and the pixel electrode and the signal electrode are formed in a manner that the distance between the pixel electrode and the signal electrode is long in the floating island region, and is short in the region above which the gate electrode is disposed.
Also, this gate electrode patterning step is characterized in that the metal film for the gate electrode is over-etched in relation to the resist mask to pattern the gate electrode.